I Designed Processing-In-Memory (PIM) DRAM circuits in Cadence Virtuoso, including key DRAM sub-blocks such as wordline decoders, sense amplifiers, precharge circuits, bitlines, memory cell arrays, and peripheral control logic. I Performed schematic design, transient simulation, and waveform…

I've Implemented the physical design of an AXI-based project using Synopsys tools (IC Compiler/Fusion Compiler), covering floorplanning, placement, clock tree synthesis, and routing. I've Worked across dual clock domains (1ns and 3ns) to close timing while meeting a strict area constraint of under…

Designed and fabricated a flexible, magnetically steerable neural interface for minimally invasive cortical signal acquisition. Developed a multilayer microfabrication process incorporating photolithography, thin-film deposition, plasma etching, polymer encapsulation, and electrode patterning.…

Designed and implemented a hardware-accelerated Convolutional Neural Network (CNN) for handwritten digit recognition on a Xilinx Arty A7-100T FPGA using Verilog, custom IP components, Vivado, and Vitis. Achieved 100% accuracy on the full 10,000-image MNIST test dataset, with an average processing…