Matrix Vector Multiplication Engine + Activation Unit
Saad Syed
OVERVIEW
• Designed and implemented a pipelined Matrix-Vector Multiplication (MVM) engine in SystemVerilog, inspired by Microsoft Brainwave’s deep learning inference accelerator.
• Optimized for throughput and latency using DSP48e1 slices, capable of calculating 27 outputs in parallel at 280 MHz.
• Built a fully pipelined hyperbolic tangent (tanh) approximation unit based on a Taylor series approximation for nonlinear activation. Improved performance from 170 MHz to 320 MHz.
HighlightS
SKILLS
SystemVerilogAMD/Xilinx VivadoPYNQ-Z1 FPGADigital Hardware DesignMachine Learning Accelerator
Saad Syed
Computer Engineering
I am a Computer Engineering student at the University of Waterloo. I specialize in FPGA development, processor design, and building scalable web applications. I combine strong technical skills with clear communication abilities, having worked as a technical writer for major technology companies while pursuing advanced coursework in computer and reconfigurable architecture and embedded systems.
I am a Computer Engineering student at the University of Waterloo. I specialize in FPGA development, processor design, and building scalable web applications. I combine strong technical skills with clear communication abilities, having worked as a technical writer for major technology companies while pursuing advanced coursework in computer and reconfigurable architecture and embedded systems.
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