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UART Transmitter in Verilog

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Mohamed Atallah

Project Timeline

Aug 2025 - Sep-2025

OVERVIEW

A UART transmitter supporting 7/8‑bit data, parity control, and 1/2 stop bits

HighlightS

  • Implemented modular components parity generator, frame generator, PISO shift register, and baud rate generator.
  • Verified functionality through extensive testbenches and waveform simulation.
  • Documented design functionality and test outputs using LaTeX.

SKILLS

VerilogSimulationQestaSim

ADDITIONAL CONTENTS

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Mohamed Atallah

Digital IC Design | Senior ECE Student

I am a senior Electrical, Electronics and Communications Engineering student at Alexandria University with a focus on hardware design and digital IC/VLSI. I have practical experience in Verilog, PCB design, and firmware development in C. My expertise spans FPGA digital design, machine learning integration with hardware, and embedded systems development. I am passionate about combining chip design with ML applications and other domain-specific hardware acceleration applications.





Skills:

Hardware Design Languages

Verilog | VHDL | SystemVerilog

Programming Languages

C/C++ | Python | MATLAB | Java | JavaScript

Hardware & Design Tools

PCB Design | Oscilloscopes | Multimeters | Spectrum Analyzers | Soldering | Laser Cutting | CAM Tools

Software Tools & Platforms

Xilinx Vivado | QuestaSim | Verilator | GTKWave | Linux | Git | LaTeX

Technical Specializations

FPGA Design | Digital IC Design | Digital Verification | Static Timing Analysis | Machine Learning | Embedded Systems