TECHNICAL SPECIFICATIONS
- S8050 NPN BJT's
- LED
- 2k2 and 1k resistors
- 9V Battery
- NAND gate only construction
DESIGN AND IMPLEMENTATION
- Initial plan and construction attempt was to build the individual 'ideal' AND, OR and XOR gates using the S8050's
- Rebuilt circuit using a NAND only construction
- Utilised circuit simulation software to verify best building techniques and expand the output from 2-bits to 3-bitsl highlighting the Carry
KEY CHALLENGES AND TROUBLESHOOTING
- The construction and cascading of the stages of 'ideal' AND, OR and XOR gates. The XOR gate is particularly difficult to construct and implement correctly, oftentimes parasitic current causing incorrect tirgering of other gates in the circuit
- The implementation of an ideal XOR gate also cause wiring complexity
- The issue was solved by implementing a NAND gate only design, which minimised the wiring complexity and number of total transistors required to complete the build
FUTURE AMENDMENTS
- Include an SR latch as a form of memory;
- Swap the button for a switch to improve use experience
- Create an embedded system to enter larger values digitally
- Create other modes for subtraction, multiplication and division