RC4 Decryption Circuit
Benjamin Heyfitch
OVERVIEW
Designed and implemented a hardware accelerator for breaking the RC4 stream cipher using a brute force approach on an FPGA. The system leverages parallel processing across four independent state machine cores, each responsible for scanning a unique segment of the keyspace. Cores coordinate with a shared datapath using a custom start-finish protocol, and halt execution once the correct key is found, optimizing both performance and resource usage.
HighlightS
SKILLS
SystemVerilogIntel Quartus PrimeModelSimFPGA
Benjamin Heyfitch
Electrical Engineering Student & Research Assistant
I am an electrical engineering student at UBC with hands-on experience in AI model optimization and FPGA design. Currently working as a research assistant, I specialize in training machine learning models on HPC clusters and developing embedded systems. My technical expertise spans from low-level hardware programming to high-level AI applications, with proven experience in SystemVerilog, Python, and microcontroller programming through various autonomous robotics and processor design projects.
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