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UART Transmitter in Verilog
Project Timeline
Aug 2025 - Sep-2025
OVERVIEW
A UART transmitter supporting 7/8‑bit data, parity control, and 1/2 stop bits
HighlightS
- Implemented modular components parity generator, frame generator, PISO shift register, and baud rate generator.
- Verified functionality through extensive testbenches and waveform simulation.
- Documented design functionality and test outputs using LaTeX.
SKILLS
VerilogSimulationQestaSim
SUPPORTING MATERIALS
Additional Details
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