RISC Machine

Developed a RISC Processor using Verilog and implemented it on an FPGA. The project involved designing a 16-bit datapath with components such as registers, an ALU, and multiplexers to perform basic arithmetic operations like addition and subtraction. A Finite State Machine (FSM) was created to control the instruction execution, automating the process and managing control signals. Instruction and data memory were integrated to enable program execution and data storage, with memory-mapped I/O implemented for communication with external hardware. Wrote testbenches for each part of the processor to ensure functional correctness through simulation.