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Altium LDO

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Arnav

Project Timeline

Aug 2025 - Sep-2025

OVERVIEW

To join WARG, I designed an LDO to learn about PCB design, component selection and the Altium Software.

HighlightS

  • Selected components from DigiKey, including a 5V to 3V3 IC, capacitors and connectors.
  • Created a symbol and footprint for the IC using datasheets and models.
  • Designed a schematic using datasheet values and added capacitors to regulate the input and output voltage
  • Considered trace width and thermal effects when designing a layout for the board
  • Ensured that resistance and inductance were minimized by placing the capacitors closer to the IC and adding stitching vias and ground pours on the top and bottom layers.

SKILLS

AltiumComponent Selection

SUPPORTING MATERIALS

Additional Media (Altium LDO)

Additional Details

Design Process

  1. Component Selection
  • Used DigiKey to find a 5V-3.3V IC.
  • Selected capacitors and resistors according to the IC's datasheet to regulate and stabilize the input and output voltage.
    PartValue / DescriptionQtyDigikey PN
    LDO ICMIC5366-3.3YC5-TR11865900
    Input Capacitor1µF, 6.3V, X7R, 06031
    GRM188R70J105KA01D
    Output Capacitor1µF, 6.3V, X7R, 06031
    GRM188R70J105KA01D
    Pull-up Resistor (EN pin)10kΩ, 06031
    RC0603FR-0710KL
    LED (Optional)Red, 06031
    LTST-C191KRKT
    LED Resistor (Optional)680Ω, 06031
    RC0603FR-07680RL
    Screw Terminal (Optional)2-pin, 3.5mm pitch1
    Phoenix Contact 1935166

    2. Symbol and footprint creation.

  • Created the LDO footprint using the IPC footprint wizard.
  • Added pads according to the documentation
  • Linked a 3D STEP model to account for vertical space
  • Created a footprint for both IC and connectors.

3. Schematic Creation

  • Added capacitors to regulate input/output voltage
  • Followed WARG guidelines to create an organized, readable schematic

Pasted image

4. Layout

  • Placed capacitors close to the IC to reduce resistance.
  • Added ground pours on top and bottom layers connected with stitching vias to reduce resistance to ground.
  • Added 15mm traces to the board to ensure thermal efficiency.
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